Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A successive approximation register analog to digital converter (ADC) typically utilizes a binary weighted capacitor array. The binary weighted capacitor array is configured to process a first reference voltage to convert the first reference voltage into a second reference voltage. The successive approximation register ADC may further include a comparator, which is configured to compare the second reference voltage against an analog input voltage. A digital output bit may be generated based on the comparison. The present disclosure has identified that various techniques that have been proposed to try to reduce the energy needed to complete the analog to digital conversion process are inadequate. Some example techniques contemplated in the present disclosure include a two step switching method, a capacitor splitting method, a charge sharing method, and a junction-splitting capacitor array method.